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Alif Semiconductor /AE302F40C1537LE_CM55_HP_View /CLKCTL_SYS /ACLK_CTRL

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Interpret as ACLK_CTRL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (Val_0x0)CLKSELECT0 (Val_0x0)CLKSELECT_CUR0ENTRY_DELAY

CLKSELECT=Val_0x0, CLKSELECT_CUR=Val_0x0

Description

SYST_ACLK Clock Control Register

Fields

CLKSELECT

Select the clock source for SYST_ACLK All other values are reserved. Selecting a reserved value can cause a deadlock.

0 (Val_0x0): Clock gated

1 (Val_0x1): SYST_REFCLK

2 (Val_0x2): SYSPLL_CLK divided by ACLK_DIV0[CLKDIV]
CLKSELECT_CUR

Currently selected clock source for SYST_ACLK All other values are reserved.

0 (Val_0x0): Clock gated

1 (Val_0x1): SYST_REFCLK

2 (Val_0x2): SYSPLL_CLK divided by ACLK_DIV0[CLKDIV]
ENTRY_DELAY

Configure number of idle clock cycles before clock is gated.

Links

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Register License

THIS SOFTWARE IS PROVIDED “AS IS”. NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. ALIF SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data